In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors for intelligent integrated systems with small latency becomes an very important subject. In this paper, we present a scheduling algorithm for high-level synthesis. The input to the scheduler is a behavioral description which is viewed as a data flow graph (DFG). The scheduler minimizes the latency, which is the delay of the critical path in the DFG, and minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the scheduler optimally assigns nodes and arcs in the DFG into steps.

This paper presents a mathematical formulation of a data path allocation and floorplanning problem using the mixed integer linear programming, and shows some experimental results. We assume that a data flow graph and the scheduled result are given in advance. The chip area and total wire length are used for the quality measures of the solution for the problem. This method is applied to some examples, and compared with the other method reported previously in the points of the solution and computation time.

The Princeton University Behavioral Synthesis System (PUBSS) performs high-level synthesis on communicating processes. The compiler accepts models written in a subset of VHDL, but performs synthesis using a more specialized model, the behavior FSMs (BFSMs), for synthesis. The simulation semantics of VHDL presents challenges in describing behavior without overly constraining that behavior solely to make the simulation work. This paper describes mismatch between the simulation semantics provided by VHDL and the synthesis semantics required for high-level synthesis and describes how we solved these problems in PUBSS.

A design system for a special purpose processor executing algorithms described by high level language is discussed. The system can generate an optimized architecture for the processor and also supply a specialized high level language compiler for the processor. A new optimization procedure is introduced to find effective functional blocks that can contribute to the improvement of performance. Functional blocks are found by simulation of the frequently appearing patterns of execution in the algorithm and used to yield a useful combined instruction.

The throughput of a parallel execution of a Digital Signal Processing (DSP) algorithm is limited by the iteration bound, which is the minimum period between the start of consecutive iterations. It is given by T=max (Ti/Di), where Ti and Di are the total time of operations and the number of delays in loop i, respectively. A schedule is said rate-optimal if its iteration period is T. The throughput of a DSP algorithm execution can be increased by reducing the Ti's, which can be done by taking as many operations as possible out of loops without changing the semantic of the calculation. This paper presents an optimization technique, called Loop Shrinking, which reduces the iteration bound this way by using commutativity, associativity and distributivity. Also, this paper presents a scheduling method, called Period-Driven Scheduling, which gives rate-optimal schedules more efficiently than existing approaches. An implementation of both is then presented for a system in development by the authors. The system shows reduction in the iteration bound near or equal to careful hand-tunning, and hardware-optimal designs in most of the cases.

This paper discusses the trends and future issues in hardware description languages (HDL's) and high-level synthesis systems. First the importance of HDL's and high-level synthesis is described. Then, several HDL's and related CAD systems are briefly introduced. Finally, the requirements to future HDL's and highlevel synthesis systems are discussed from several points of view.